1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a low-resistive gate electrode which is capable of preventing reduction in an operation speed of a semiconductor device, and a method of fabricating such a low-resistive gate electrode.
2. Description of the Related Art
In a field of a semiconductor device such as a large-scale integrated (LSI) circuit, various proposals have been made in order to accomplish reduction in an electrical resistance of a gate electrode.
For instance, there has been suggested a metal gate structure comprised of a gate electrode formed on a gate oxide film and composed of a metal such as aluminum (Al).
The metal gate structure makes it possible to reduce an electrical resistance in a gate electrode. However, the metal gate structure is accompanied with a problem of reduction n a resistance to heat. This causes another problem that annealing at a high temperature for enhancing reliability and performance of a transistor cannot be carried out after formation of a gate electrode.
There has been suggested a silicon gate structure comprised of an impurity-doped polysilicon (DOPOS) layer formed on a gate oxide film formed at a surface of a semiconductor substrate.
The silicon gate structure presents an advantage that a gate electrode can be formed subsequently to the formation of a gate oxide film in an initial stage in a process of fabrication of a semiconductor device, and hence, it would be possible to prevent the gate oxide film from being contaminated with dust. However, the silicon gate structure is accompanied with a problem that there is a limit in reduction in an electrical resistance in a gate electrode because of a high layer or sheet resistance.
Hence, in order to further reduce an electrical resistance of a gate electrode, there has been suggested a polycide gate comprised of a refractive metal silicide layer such as a tungsten silicide (WSi2), formed on a thin DOPOS layer formed on a gate oxide film. Since the polycide gate could be fabricated to have a lower electrical resistance and further a higher resistance to heat than those of the above-mentioned silicon gate structure. Thus, a polycide gate is selected in fabrication of a MOS device in these days.
In order to further reduce an electrical resistance of a gate electrode, there has been further suggested a polymetal gate structure comprised of a refractive metal layer such as a tungsten layer, formed on a thin DOPOS layer formed on a gate oxide film.
The polymetal gate makes it possible to make a sheet resistance smaller than the above-mentioned silicon gate structure and polycide gate, which ensures enhancement in a response speed in a semiconductor device such as a MOS device. However, the polymetal gate is accompanied with a problem that a refractive metal layer would react with a DOPOS layer in a process of thermally annealing at a high temperature, resulting in that an impurity concentration of the DOPOS layer would be reduced, and further, metal atoms are diffused out of the refractive metal layer.
In order to solve this problem, Japanese Patent Application Publication No. 11-233451 which is based on U.S. patent application Ser. No. 061557 filed on Oct. 7, 1997 by Texas Instrument Incorporated has suggested a gate electrode which is capable of suppressing reaction in a process of thermally annealing at a high temperature. The suggested gate electrode is designed to include a refractive metal nitride layer such as a tungsten nitride (WN) layer, sandwiched between a refractive metal layer and a DOPOS layer.
In fabrication of the suggested gate electrode, a process of thermally annealing is carried out after the formation of a refractive metal nitride layer on a DOPOS layer. This removes nitrogen excessively contained in the refractive metal nitride layer, and converts the refractive metal nitride layer in composition into a refractive metal silicide nitride layer such as WSiN.
However, if a process of thermally annealing is carried out after a refractive metal nitride layer has been formed on the DOPOS layer, the refractive metal nitride layer highly reacts with silicon existing in the DOPOS layer, resulting in that there is formed a thick refractive metal silicide nitride layer. Though a refractive metal silicide nitride layer well acts as a barrier, it has a high interface resistance in dependence on its composition or a structure of layered films, resulting in a resultant gate electrode would have a high electrical resistance. Accordingly, a thicker refractive metal silicide nitride layer would make is more difficult to reduce an electrical resistance of a gate electrode.
FIGS. 1A to 1C are cross-sectional views of a gate electrode having a polycide gate structure, illustrating respective steps in a process of fabricating the gate electrode.
As illustrated in FIG. 1C, a gate electrode 50 is comprised of a DOPOS layer 53 formed on a silicon dioxide film 52 formed at a surface of a silicon substrate 51 as a gate oxide film, a WSi2 layer 54 formed on the DOPOS layer 53, a SiN layer 55 formed on the WSi2 layer 54, an oxide film 56a covering sidewalls of the DOPOS layer 53 and the WSi2 layer 54 therewith, and a sidewall 57 covering the oxide film 56a and a sidewall of the SiN layer 55 therewith.
Hereinbelow is explained a process of fabricating the gate electrode 50 illustrated in FIG. 1C.
As illustrated in FIG. 1A, a multi-layered structure 59 comprised of the DOPOS layer 53, the WSi2 layer 54 and the SiN layer 55 is formed on the silicon substrate 51. Then, the multi-layered structure 59 is thermally annealed in an oxygen atmosphere, that is, rapid thermal oxidation (RTO) is carried out to the multi-layered structure 59. Thus, as illustrated in FIG. 1B, the DOPOS layer 53 and the WSi2 layer 54 are oxidized at their sidewalls with the result that the oxide film 56a is formed around the sidewalls, and the silicon substrate 51 is partially oxidized with the result that an oxide film 56b is formed in the silicon substrate 51 under the silicon dioxide film 52.
Then, areas of the silicon substrate 51 in which NMOS and PMOS transistors are to be formed are covered with a resist film. Then, ion implantation is carried out to the silicon substrate 51 with the multi-layered structure 59 including the oxide film 56a, being used as a mask.
Specifically, arsenic (As) is implanted into an area where an NMOS transistor is to be formed, and BF2 is implanted into an area where a PMOS transistor is to be formed, for instance. As a result, a lightly-doped ion-implanted layer 58a having LDD (low-doped-drain) structure is formed in the silicon substrate 51 in dependence on the multi-layered structure 59.
Then, for instance, a silicon nitride film is formed entirely over the multi-layered structure 59. By etching back the silicon nitride film, the sidewall 57 is formed on a sidewall of the multi-layered structure 59, as illustrated in FIG. 1C.
Then, the areas in which NMOS and PMOS transistors are to be formed are covered with a resist film. Then, ion implantation is carried out to the silicon substrate 51 with the multi-layered structure 59 including the sidewall 57, being used as a mask, similarly to the formation of the lightly-doped ion-implanted layer 58a. As a result, a heavily-doped diffusion layer 58b is formed in the silicon substrate 51.
The gate electrode 50 having such a polycide gate structure as mentioned above has advantages that it can recover damages of the silicon substrate 51 caused by gate etching and ion implantation, and has a sufficient resistance to thermally annealing necessary for activating impurities having been implanted into the silicon substrate 51.
However, the gate electrode 50 is accompanied with problems as follows.
With a requirement of reduction in a size of a transistor, a self-align contact (SAC) structure is frequently used for arranging wirings in a transistor.
In order to accomplish a SAC structure, it is necessary to form the sidewall 57 comprised of a silicon nitride (SiN) film around a sidewall of the multi-layered structure 59, as illustrated in FIG. 1C. If the sidewall 57 comprised of a silicon nitride (SiN) film is formed directly on a sidewall of the DOPOS layer 53, a resultant transistor would have a reduced resistance to hot electron, resulting in deterioration in reliability of a transistor. Accordingly, in general, the sidewall 57 comprised of a silicon nitride (SiN) film is formed around the multi-layered structure 59 after the DOPOS layer 53 has been oxidized at a sidewall thereof.
If a gate electrode is thermally annealed in a furnace at a high temperature for long time (for instance, at 1000 degrees centigrade for 1 hour) in order to oxidize a sidewall of the DOPOS layer 53, impurities implanted into the silicon substrate 51 are horizontally diffused, resulting in that it would become quite difficult to form a transistor in a small size, and that integration of a transistor would be reduced. Hence, rapid thermal oxidation (RTO) is generally carried out by means of a ramp annealer, for instance, for oxidizing a sidewall of the DOPOS layer 53. Rapid thermal oxidation can oxidize a sidewall of the DOPOS layer 53 at a moment.
An oxidation rate of the silicon substrate 51 is smaller than oxidation rates of the DOPOS layer 53 and the WSi2 layer 54. In other words, sidewalls of the DOPOS layer 53 and the WSi2 layer 54 are more easily oxidized than the silicon substrate 51. Hence, if rapid thermal oxidation is carried out immediately after the formation of the multi-layered structure 59, sidewalls of the DOPOS layer 53 and the WSi2 layer 54 would horizontally project, as illustrated in FIG. 1B. The WSi2 layer 54 is particularly likely to be oxidized. Since crystal grains grow in oxidation of the WSi2 layer 54, the oxide film 56a projects in a shape of an arc on a sidewall of the WSi2 layer 54.
As a result that the oxide film 56a projects on a sidewall of the WSi2 layer 54, the lightly-doped ion-implanted layer 58ais formed merely in an area starting from a location located just below a summit of the projecting oxide film 56a. This results in that a designed gate length L1 would become an actual length L2 longer than the length L1. That is, a gate length would become longer than designed. Such unexpected extension in a gate length would prevent a transistor from being fabricated in a small size, and would significantly deteriorate reliability of a transistor.
In addition, the projecting oxide film 56a causes the following problems.
FIG. 2 is a cross-sectional view of a transistor, illustrating a step to be carried out subsequently to the step illustrated in FIG. 1C.
After the sidewall 57 has been formed on a sidewall of the multi-layered structure 59, an interlayer insulating film 60 is formed all over the silicon substrate 51.
Then, contact holes are formed throughout the interlayer insulating film 60 by photolithography and dry etching. Then, metal or polysilicon is buried in each of the contact holes to thereby form contact plugs 61.
After the interlayer insulating film 60 has been planarized at a surface thereof, a wiring layer 62 is formed on the interlayer insulating film 60.
Since an arc shape of the oxide film 56a is reflected to a shape of the sidewall 57 formed on the oxide film 56a, the sidewall 57 also horizontally projects due to a portion of the oxide film 56a covering the WSi2 layer 54 therewith.
As a result, when the interlayer insulating film 60 is formed, there are generated voids 63 caused by defect in deposition of the interlayer insulating film 60, between the sidewalls 57 of the adjacent gate electrodes 50. Since the voids 63 are filled with a material of which the contact plug 61 is composed, such as metal or polysilicon, there is caused a problem that contact holes located adjacent to each other ill a longitudinal direction (a direction perpendicular to a plane of FIG. 2) of the gate electrode 50 might be short-circuited with each other.
Japanese Patent Application Publication No. 8-321613 has suggested a method of fabricating a semiconductor device, including the steps of forming a gate oxide film at a surface of a semiconductor substrate, forming a polysilicon film on the gate oxide film, forming a refractive metal silicide film on the polysilicon film, patterning the refractive metal silicide film and the polysilicon film to thereby form a gate electrode, ion-implanting nitrogen obliquely into the gate electrode while the gate electrode is in rotation, and oxidizing the gate electrode.
Japanese Patent Application Publication No. 9-307106 has suggested a method of fabricating a semiconductor device, including the steps of forming a first electrically insulating layer on a semiconductor substrate, forming a polysilicon film on the first electrically insulating layer, patterning the polysilicon film into a gate electrode of a MOS transistor, and nitriding the semiconductor substrate to thereby form a silicon nitride film around a sidewall of the gate electrode.
However, the above-mentioned problems remain unsolved even in the above-mentioned Japanese Patent Application Publications.